1. Field of the Invention
The present invention relates to a method of forming an isolation film in a semiconductor device, and more particularly, to a method of forming an isolation film in a semiconductor device capable of preventing a junction leakage in the semiconductor device.
2. Background of the Related Art
A junction leakage in semiconductor devices causes to not only increase the standby current of a logical device, thus consuming lots of the power but also degrade a retention (refresh margin reduction) characteristic of the semiconductor device having memory cells.
A cause of the reverse biased junction leakage, which has been well known in the art, is generation current (Igen) due to electron-hole creation and recombination at the space charge region or the depletion region of semiconductor junctions (PN or NP) of opposite types (“MOSFET Models for VLSI Circuit Simulation Theory and Practice”, Narain Arora, p50˜51), as shown in FIG. 1.
This generation current (Ign) is principally generated due to thermal activation even at ideal semiconductors having no any defect. This could be controlled by only changing the type of the semiconductor substrate. However, additional electron and hole trap (or creation) centers are created due to various kinds of semiconductor device defects (vacancy, interstitial and dislocation, which cause lattice defect of the substrate, a dangling bond existing at the interface of the semiconductor substrate and the insulating film, and the like) that are caused by the process of manufacturing the semiconductor device. These cause to significantly increase the junction leakage.
An effort to minimize the junction leakage has been made generally and widely on the device manufacture processes of all the kinds including an implantation process for controlling the concentration of the substrate, an annealing process, a cleaning process, an etch process, a deposition process for minimizing a film stress, and the like. Further, it was known that a main location where the junction leakage occurred is collectively distributed at a boundary region of the semiconductor substrate and the isolation insulating film upon a shallow trench isolation (STI) process (LOCOS, local oxidation of silicon). Due to this, it is common to include various complicated cleaning, oxidization, etch processes, etc. for reducing defects in this region. As one example, in the method of manufacturing the cell transistor for manufacturing a DRAM memory cell, an effort for improving the retention characteristic of the DRAM by making different the junction structure of the source and drain is in progress. (Novel DRAM Cell Transistor With Asymmetric Source and Drain Junction Profiles Improving Data Retention Characteristics”, S. J. Ahn, 2002 Symposium on VLSI Technology Digest of Technical Papers, p176). However, this method has problems that it is more complicated than the existing method, unnecessarily increases the number of process and thus increases the production period and cost. Further, this method does not fundamentally remove the semiconductor substrate defect generated at the boundary region of the isolation insulating film and the semiconductor region. Accordingly, this method could be not a solution to fundamentally remove the junction leakage.